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HIP4086, HIP4086A
Typical Performance Curves (Continued)
6
RDEL = 100k ?
11.0
10.5
10.0
4
9.5
9.0
8.5
ENABLE (50k ? , UVLO TO GND)
TRIP (50k, UVLO TO GND)
2
RDEL = 10k ?
8.0
7.5
7.0
6.5
T RIP/ENABLE           (0k ? , UVLO TO V DD )
ENABLE (UVLO OPEN)
TRIP (UVLO OPEN)
0
-60
-40
-20
0
20
40
60
80
100
120
140
160
6.0
-60
-40
-20
0
20
40
60
80
100
120
140 160
JUNCTION TEMPERATURE (°C)
FIGURE 18. DEAD TIME
JUNCTION TEMPERATURE (°C)
FIGURE 19. UNDERVOLTAGE THRESHOLD
25
V xHS = 80V
20
15
10
-60
-40
-20
0
20
40
60
80
100
120
140
160
JUNCTION TEMPERATURE (°C)
FIGURE 20. I xHS LEAKAGE CURRENT
Functional Description
Input Logic
NOTE: When appropriate for brevity, input and output pins will be
prefixed with an “x” as a substitute for A, B, or C. For example,
xHS refers to pins AHS, BHS, and CHS.
The HIP4086/A is a three phase bridge driver designed
specifically for motor drive applications. Three identical half
bridge sections, A, B, and C, can be controlled individually by
their input pins, ALI, AHI, BLI, BHI, and CLI, CHI (xLI, xHI) or the 2
corresponding input pins for each section can be tied together to
form a PWM input (xLI connected to xHI = xPWM). When
controlling individual inputs, the programmable dead time is
optional but shoot-thru protection must then be incorporated in
the timing of the input signals. If the PWM mode is chosen, then
the internal programmable dead time must be used.
Shoot-Thru Protection
Dead time, to prevent shoot-thru, is implemented by delaying the
turn-on of the high-side and low-side drivers. The delay timers are
10
enabled if the voltage on the RDEL pin is greater than 100mV.
The voltage on RDEL will be greater than 100mV for any value of
programming resistor in the specified range. If the voltage on
RDEL is less than 100mV, the delay timers are disabled and no
shoot-thru protection is provided by the internal logic of the
HIP4086/A. When the dead time is to be disabled, RDEL should
be shorted to VSS.
Refresh Pulse
To insure that the boot capacitors are charged prior to turning on
the high-side drivers, a refresh pulse is triggered when DIS is low
or when the UV comparator transitions low (VDD is greater than
the programmed undervoltage threshold). Please refer to the
“Block Diagram (for clarity, only one phase is shown)” on page 2.
When triggered, the refresh pulse turns on all of the low-side
drivers (xLO = 1) and turns off all of the high-side drivers
(xHO = 0) for a duration set by a resistor tied between RDEL and
VSS. When xLO = 1, the low-side bridge FETs charge the boot
caps from VDD through the boot diodes.
FN4220.9
February 1, 2013
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